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 DIFFERENTIAL CLOCK D FLIP-FLOP
DESCRIPTION
SY10EL51 SY100EL51
FEATURES
s s s s 475ps propagation delay 2.8GHz toggle frequency Internal 75K input pull-down resistors Available in 8-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
R D CLK CLK
1 R 2 3 4 D Flip-Flop
8 7 6 5
VCC Q Q VEE
The SY10/100EL51 are differential clock D flip-flops with reset. These devices are functionally similar to the E151 devices, with higher performance capabilities. With propagation delays and output transition times significantly faster than the E151, the EL51 is ideally suited for those applications which require the ultimate in AC performance. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EL51 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input (pulled down to VEE) conditions.
SOIC TOP VIEW
PIN NAMES
Pin R D CLK Q Function Reset Input Data Input Clock Input Data Output
TRUTH TABLE(1)
D L H X R L L H CLK Z Z X Q L H L
NOTE: 1. Z = LOW-to-HIGH transition.
Rev.: E
Amendment: /0
1
Issue Date: August, 1998
Micrel
SY10EL51 SY100EL51
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = -40C Symbol IEE Parameter Power Supply Current 10EL 100EL Min. -- -- Typ. 24 24 -5.2 -4.5 -- Max. 29 29 -5.5 -5.5 150 Min. 19 19 -4.75 -4.20 -- TA = 0C Typ. 24 24 -5.2 -4.5 -- Max. 29 29 -5.5 -5.5 150 TA = +25C Min. 19 19 -4.75 -4.20 -- Typ. 24 24 -5.2 -4.5 -- Max. 29 29 -5.5 -5.5 150 Min. 19 24 -4.75 -4.20 -- TA = +85C Typ. 24 30 -5.2 -4.5 -- Max. 29 36 V -5.5 -5.5 150 A Unit mA
VEE
Power Supply Voltage 10EL -4.75 100EL -4.20 Input HIGH Current --
IIH
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = -40C Symbol fMAX tPLH tPHL tS tH tRR tPW VPP VCMR tr tf Parameter Maximum Toggle Frequency Propagation Delay to Output CLK R Set-up Time Hold Time Reset Recovery Minimum Pulse Width CLK, Reset Minimum Input Swing(1) Common Mode Range(2) Min. Typ. 1.8 2.8 Max. -- Min. 2.2 TA = 0C Typ. 2.8 Max. -- Min. 2.2 TA = +25C Typ. 2.8 Max. -- 2.2 TA = +85C Min. Typ. 2.8 Max. -- Unit GHz ps 325 305 150 250 400 400 150 (2) 465 455 0 100 200 -- -- -- 225 605 605 -- -- -- -- -- -0.4 350 375 355 150 250 400 400 150 (2) 100 465 455 0 100 200 -- -- -- 225 555 555 -- -- -- -- -- -0.4 350 385 355 150 250 400 400 150 (2) 100 475 465 0 100 200 -- -- -- 225 565 565 -- -- -- -- -- -0.4 350 440 410 150 250 400 400 150 (2) 100 530 510 0 100 200 -- -- -- 225 620 620 -- -- -- -- -- -0.4 350 ps ps ps ps mV V ps
Output Rise/Fall Times Q 100 (20% to 80%)
NOTES: 1. Minimum input swing for which AC parameters are guaranteed. 2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP min. and 1V. The lower end of the CMR range is dependent on VEE and is equal to VEE + 3.0V.
PRODUCT ORDERING CODE
Ordering Code SY10EL51ZC SY10EL51ZCTR SY100EL51ZC SY100EL51ZCTR Package Type Z8-1 Z8-1 Z8-1 Z8-1 Operating Range Commercial Commercial Commercial Commercial
2
Micrel
SY10EL51 SY100EL51
8 LEAD SOIC .150" WIDE (Z8-1)
Rev. 03
3
Micrel
SY10EL51 SY100EL51
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
FAX
+ 1 (408) 980-9191
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated
4


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